1. Field of the Invention
The invention in general relates to electronic circuit testing and more particularly to an apparatus and testing method utilizing an enhanced test data compression technique.
2. Statement of the Problem
The testing of electrical circuits is nearly as old as electrical circuits themselves. In simple circuits this is done by applying small voltages to all the circuit nodes to test for shorts or open circuits. The term node in this specification means any equipotential circuit element; an example is a connecting wire or trace between two electrical components. As circuits have become more complex, it has become ever more important and more difficult to thoroughly test circuits. A common way of doing this is to design a testing apparatus and method as part of the development program for each of the circuit boards that are manufactured as part of a product. Generally a program is developed which operates a complex testing machine that includes hundreds or even thousands of resources, such as voltage drivers and receivers, relays, and tester pins. The drivers and receivers are alternately connected in a programmed, clocked, sequence to the nodes of the device under test (DUT) via the relays and the tester pins which contact test connectors, such as the edge connectors of a board or conducting nails in a nail bed attached to a device under test. In a typical clock period of the programmed sequence, the drivers will force the tester pins contacting certain ones of the nodes of the DUT to prescribed voltages and check that the receivers connected to other tester pins contacting other certain ones of the nodes receive the proper output signals that should be received if the DUT is functioning correctly. If at any clock cycle in the sequence, the proper output signals are not received, the DUT is deemed defective, the defective nodes are recorded or otherwise indicated by the tester, and the test is terminated. The set of digital signals transmitted and received to and from the tester pins on a given clock cycle is called a test vector.
The data signals transmitted and received in a digital test can be effectively viewed as a large matrix of binary data: each of the columns of the matrix being associated with a test pin, and each of the rows of the matrix corresponding to the test vector at a given clock cycle of the tester. This matrix must be stored in some fashion and communicated to the tester during the test. Generally, it is stored on disk or tape or other non-volatile electronic storage device and loaded into RAMs forming part of the tester prior to the test. The complete matrix including the test vectors for each clock cycle of the test is called the "flattened" or "unrolled" form of the test matrix. Storing and using this flattened or unrolled form of the matrix is very RAM intensive and very expensive. Therefore, state-of-the-art digital testers include an electronic system that stores the matrix in a compressed form. See for example, U.S. Pat. No. 4,652,814 which describes a system in which only the unique test vectors are stored in the tester RAMs, and a sequencer stores the sequence of test vectors in the form of processor subroutines, loops, etc. During the test, the sequencer calls up the proper test vectors in sequence, thus constructing the flattened form of the test on-the-fly from the compressed data.
As electronic devices have become more and more complex, the number of connector pins on circuit boards have become very large. There may be as many as a hundred or more such connectors. The number of test pins required to test a circuit board has grown commensurately. As the number of test pins, and thus the size of the test vector, becomes large, it becomes more and more difficult to compress a test. This is because the compression techniques look for sections of a test that are reusable. For example, a sequence of vectors, A, B, C, may recur often in a test, and compression can take advantage of this by storing them once, and reusing them. However, as test vector becomes larger, the chances of it recurring decrease. That is, if only ten pins are used in a test, the chances of identical digital voltages being found on them at different times in a given test is much greater than if a hundred pins are used in a test. Thus, there is a need for a compression technique that is more effective for testers with large test vectors, that is, with large numbers of test pins.